| Feature | Value / Description |
|---|---|
| Slot Structure | 8-slot: 1× Power, 1× SBC, 1× Switch, 1× Clock, 3–5× Payload |
| Data Plane | PCIe Gen3 x4/x8 — switch-centered fabric (40GBASE-KR4 option) |
| Control Plane | 10GBASE-KR4 Ethernet |
| Expansion Plane | UTP 10GBASE-KR — optional secondary data plane |
| Clock Plane | Radial low-jitter clock distribution — via P1 connector |
| Management | IPMB-A/B, VITA 46.11 compliant, IPMI (I2C-based chassis management) |
| Power Rails | +12V, +3.3V, +5V, ±12V AUX (VITA 62 approach) |
| RF Expansion (P2) | VITA 67.3 — nano-coax (up to 20×) or optical MT connector |
| Debugging | Includes JTAG chain |